? semiconductor components industries, llc, 2012 august, 2012 ? rev. 1 1 publication order number: NTLUD3A50PZ/d NTLUD3A50PZ power mosfet ? 20 v, ? 5.6 a, cool dual p ? channel, 2.0x2.0x0.55 mm udfn package features ? udfn package with exposed drain pads for excellent thermal conduction ? low r ds(on) ? low profile udfn 2.0x2.0x0.55 mm for board space saving ? these devices are pb ? free, halogen free/bfr free and are rohs compliant applications ? high side load switch ? reverse current protection ? battery switch ? optimized for power management applications for portable products, such as cell phones, pmp, dsc, gps, and others maximum ratings (t j = 25 c unless otherwise stated) parameter symbol value units drain-to-source voltage v dss ? 20 v gate-to-source voltage v gs 8.0 v continuous drain current (note 1) steady state t a = 25 c i d ? 4.4 a t a = 85 c ? 3.2 t 5 s t a = 25 c ? 5.6 power dissipa- tion (note 1) steady state t a = 25 c p d 1.4 w t 5 s t a = 25 c 2.2 continuous drain current (note 2) steady state t a = 25 c i d ? 2.8 a t a = 85 c ? 2.0 power dissipation (note 2) t a = 25 c p d 0.5 w pulsed drain current tp = 10 s i dm ? 13 a operating junction and storage temperature t j , t stg -55 to 150 c source current (body diode) (note 2) i s ? 1.0 a lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. surface mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [1 oz] including traces) based on both fets on. 2. surface-mounted on fr4 board using the minimum recommended pad size of 30 mm 2 , 1 oz. cu based on both fets on. http://onsemi.com ? 20 v 70 m @ ? 2.5 v 50 m @ ? 4.5 v r ds(on) max i d max v (br)dss mosfet see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information aa = specific device code m = date code = pb ? free package aa m 1 115 m @ ? 1.8 v marking diagram 175 m @ ? 1.5 v (top view) (note: microdot may be in either location) ? 5.6 a g1 s1 p ? channel mosfet d1 udfn6 case 517bf cool g2 s2 d2 1 6
NTLUD3A50PZ http://onsemi.com 2 thermal resistance ratings parameter symbol max units junction-to-ambient ? steady state (note 3) r ja 91 c/w junction-to-ambient ? t 5 s (note 3) r ja 57 junction-to-ambient ? steady state min pad (note 4) r ja 228 electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max units off characteristics drain-to-source breakdown voltage v (br)dss v gs = 0 v, i d = ? 250 a ? 20 v drain-to-source breakdown voltage temperature coefficient v (br)dss /t j i d = ? 250 a, ref to 25 c ? 13 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = ? 20 v t j = 25 c ? 1.0 a gate-to-source leakage current i gss v ds = 0 v, v gs = 5.0 v 5.0 a on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = ? 250 a ? 0.4 ? 1.0 v negative threshold temp. coefficient v gs(th) /t j 3.0 mv/ c drain-to-source on resistance r ds(on) v gs = ? 4.5 v, i d = ? 4.0 a 37 50 m v gs = ? 2.5 v, i d = ? 3.0 a 46 70 v gs = ? 1.8 v, i d = ? 2.0 a 63 115 v gs = ? 1.5 v, i d = ? 1.0 a 86 175 forward transconductance g fs v ds = ? 5.0 v, i d = ? 3.0 a 16 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1 mhz, v ds = ? 15 v 920 pf output capacitance c oss 85 reverse transfer capacitance c rss 80 total gate charge q g(tot) v gs = ? 4.5 v, v ds = ? 15 v; i d = ? 3.0 a 10.4 nc threshold gate charge q g(th) 0.5 gate-to-source charge q gs 1.2 gate-to-drain charge q gd 3.0 switching characteristics, vgs = 4.5 v (note 6) turn-on delay time t d(on) v gs = ? 4.5 v, v dd = ? 15 v, i d = ? 3.0 a, r g = 1 7.0 ns rise time t r 12 turn-off delay time t d(off) 39 fall time t f 30 drain-source diode characteristics forward diode voltage vsd v gs = 0 v, i s = ? 1.0 a t j = 25 c ? 0.67 ? 1.0 v t j = 125 c ? 0.56 reverse recovery time t rr v gs = 0 v, dis/dt = 100 a/ s, i s = ? 1.0 a 12.1 ns charge time t a 6.4 discharge time t b 5.7 reverse recovery charge q rr 4.0 nc 3. surface-mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [1 oz] including traces) based on both fets on. 4. surface-mounted on fr4 board using the minimum recommended pad size of 30 mm 2 , 1 oz. cu based on both fets on. 5. pulse test: pulse width 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures.
NTLUD3A50PZ http://onsemi.com 3 typical characteristics figure 1. on ? region characteristics figure 2. transfer characteristics ? v ds , drain ? to ? source voltage (v) ? v gs , gate ? to ? source voltage (v) figure 3. on ? resistance vs. gate ? to ? source voltage figure 4. on ? resistance vs. drain current and gate voltage ? v gs , gate voltage (v) ? i d , drain current (a) figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) ? v ds , drain ? to ? source voltage (v) ? i d , drain current (a) ? i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , normalized drain ? to ? source resistance ( ) ? i dss , leakage (na) v gs = ? 2.5 v ? 3.0 v ? 4.5 to ? 3.5 v ? 1.5 v v ds = ? 5 v t j = 25 c t j = ? 55 c t j = 125 c i d = ? 4.0 a t j = 25 c r ds(on) , drain ? to ? source resistance ( ) t j = 25 c ? 1.8 v ? 2.5 v v gs = ? 4.5 v v gs = ? 4.5 v i d = ? 4.0 a t j = 85 c t j = 125 c 100 1000 10000 100000 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ? 1.8 v ? 2 v 0 2 4 6 8 10 12 14 16 18 20 0.5 1 1.5 2 2.5 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 2 4 6 8 10 12 14 16 18 ? 1.5 v 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 ? 50 ? 25 0 25 50 75 100 125 150 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 20
NTLUD3A50PZ http://onsemi.com 4 typical characteristics figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge ? v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) ? v sd , source ? to ? drain voltage (v) figure 11. threshold voltage t j , junction temperature ( c) c, capacitance (pf) ? v gs , gate ? to ? source voltage (v) t, time (ns) ? i s , source current (a) ? v gs(th) (v) v gs = 0 v t j = 25 c f = 1 mhz c iss c oss c rss v ds = ? 15 v i d = ? 3.0 a t j = 25 c v ds v gs q gs q gd ? v ds , drain ? to ? source voltage (v) v gs = ? 4.5 v v dd = ? 15 v i d = ? 3.0 a t d(off) t d(on) t f t r t j = 25 c t j = ? 55 c t j = 125 c i d = ? 250 a 1.0 10 100 1000 1 10 100 0.1 1.0 10.0 50 25 0 25 50 75 100 125 150 0 200 400 600 800 1000 1200 1400 1600 1800 0 2 4 6 8 10 12 14 16 18 20 0 3 6 9 12 15 18 0 1 2 3 4 5 024681012 q t 0.3 0.4 0.6 0.8 1.0 1.1 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85 figure 12. maximum rated forward biased safe operating area ? v ds , drain ? to ? source voltage (v) ? i d , drain current (a) 0.01 0.1 1 10 100 0.1 1 10 100 0 v gs ? 8 v single pulse t c = 25 c r ds(on) limit thermal limit package limit 100 s 1 ms 10 ms dc 0.5 0.7 0.9
NTLUD3A50PZ http://onsemi.com 5 typical characteristics figure 13. fet thermal response t, time (s) r(t), effective transient thermal response ( c/w) r ja = 91 c/w steady state single pulse duty cycle = 0.5 0.2 0.1 0.05 0.02 0.01 1e+00 1e+01 1e+02 1e+03 1e ? 06 1e ? 05 1e ? 04 1e ? 03 1e ? 02 1e ? 01 0 10 20 30 40 50 60 70 80 90 100 device ordering information device package shipping ? NTLUD3A50PZtag udfn6 (pb ? free) 3000 / tape & reel NTLUD3A50PZtbg udfn6 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NTLUD3A50PZ http://onsemi.com 6 package dimensions udfn6 2x2, 0.65p case 517bf issue b notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d e 0.10 c a3 a a1 0.10 c dim a min max millimeters 0.45 0.55 a1 0.00 0.05 a3 0.13 ref b 0.25 0.35 d 2.00 bsc d2 0.57 0.77 0.90 1.10 e 2.00 bsc 0.25 ref e2 e 0.65 bsc k 0.20 0.30 l 0.15 bsc f pin one reference 0.08 c 0.10 c note 4 a 0.10 c note 3 l e d2 e2 b b 3 6 6x 1 k 4 0.05 c d2 f bottom view l1 detail a l optional constructions ??? ?? ?? --- 0.10 l1 a 0.10 cb a 0.10 cb mounting footprint recommended dimensions: millimeters 6x 0.47 2.30 1.10 0.77 2x 1.74 0.65 pitch 6x 0.35 1 package outline on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NTLUD3A50PZ/d cool is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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